Many integrated circuits (“ICs”) are made up of millions of interconnected devices, such as transistors, resistors, capacitors, and diodes, on a single chip of semiconductor substrate. It is generally desirable that ICs operate as fast as possible, and consume as little power as possible. Semiconductor ICs often include one or more types of memory, such as CMOS memory, antifuse memory, and efuse memory.
Efuses are usually integrated into semiconductor ICs by using a stripe (commonly also called a “link”) of conducting material (metal, poly-silicon, etc.) between two pads, generally referred to as anode and cathode, so that at a fuse current level (IFUSE) the stripe of conducting material is thermally destroyed, thus changing the resistance of the efuse stripe. This is commonly referred to as “programming” the efuse. The fuse state (i.e., whether it has been programmed) can be read using a sensing circuit, which are common in the art of electronic memories.
Unfortunately, other portions of the IC can be damaged under certain efuse programming conditions, which can lead to circuit damage, reliability issues, and even failure of the IC. Damage resulting from efuse programming can occur in the “front end” of the IC, namely in the substrate and structures typically associated with the transistors and other devices formed on a semiconductor substrate, or in the “back end” of the IC, which is generally the patterned metal layers and inter-metal dielectric overlying the front end of the IC that interconnect the devices.
IC damage occurring from programming an efuse can result from improper programming by the user. Proper efuse programming conditions depend on a number of factors, and proper efuse programming parameters are usually determined during the design and development phase of an IC. Conventional techniques for evaluating damage occurring as a result of efuse programming include identifying a damaged area, processing the IC to expose a cross section of the IC that intersects the damaged area, and looking for the damage using a scanning electron microscope (“SEM”) or similar evaluation methods. Unfortunately, such techniques are time consuming, expensive, require considerable skill, and result in the destruction of the IC. In some cases, efuse programming damage is masked or exacerbated by the sample preparation. Similarly, some efuse damage results in “soft” failures, such as inter-layer current leakage or metal migration, that causes operational or reliability problems with the IC, and can not be identified using conventional techniques.
It is desirable to provide techniques for evaluating efuse programming damage in an IC that avoids limitations of conventional techniques.